The dominant semiconductor fabrication technology used for the manufacture of the ultra-large scale integrated (USLI) circuits is the metal-oxide-semiconductor field effect transistor (MOSFET) technology. Reduction in the size of MOSFETs has provided continued improvement in speed performance, circuit density, and cost per unit function over the past few decades. As the gate length of the conventional bulk MOSFET is reduced, the source and drain increasingly interact with the channel and gain influence on the channel potential. Consequently, a transistor with a short gate length suffers from problems related to the inability of the gate to substantially control th on and off states of the channel. Phenomena such as reduced gate control associated with transistors with short channel lengths are termed short-channel effects. Increased body doping concentration, reduced gate oxide thickness, and ultra-shallow source/drain junctions are ways to suppress short-channel effects in the conventional bulk MOSFET. However, for device scaling well into the sub-50 nm regime, the requirements for body-doping concentration, gate oxide thickness, and source/drain (S/D) doping profiles become increasingly difficult to meet when conventional device structures based on bulk silicon (Si) substrates are employed. Innovations in front-end-process technologies or the introduction of alternative device structures are required to sustain the historical pace of device scaling.
A promising approach to controlling short-channel effects is to use an alternative device structure with a multiple-gate. Examples of multiple-gate structures include the double-gate structure, the triple-gate structure, the omega-FET structure, and the surround-gate or wrap-around gate structure. A multiple-gate transistor structure is expected to extend the scalability of CMOS technology beyond the limitations of the conventional bulk MOSFET and realize the ultimate limit of silicon MOSFETs. The introduction of additional gates improves the capacitance coupling between the gates and the channel, increases the control of the channel potential by the gate, helps suppress short channel effects, and prolongs the scalability of the MOS transistor.
An example of a multiple-gate device is the double-gate MOSFET structure, where there are two gate electrodes on the opposing sides of the channel or silicon body. A manufacturable way to fabricate a double-gate MOSFET is descried by U.S. Pat. No. 6,413,802B1, issued to Hu et al, as shown in FIGS. 1A–1C for a FinFET transistor structure 10 having a double-gate electrode 12 extending vertically from a substrate 14 and method of manufacture. In U.S. Pat. No. 6,413,802B1, the device channel comprises a thin silicon fin 20 formed on an insulating substrate 16 (i.e. silicon oxide) and defined using an etchant mask 18. The etchant mask 18 of U.S. Pat. No. 6,413,802B1 is retained on the fin 20 in the channel region throughout the process. Gate oxidation is performed, followed by gate deposition and gate patterning to form the gate electrode 12 that straddles across the fin 20 with a gate dielectric layer 26 in-between. A three-dimensional perspective view of this device structure is illustrated in FIG. 1A. Both the source-to-drain directions and the gate-to-gate directions are in the plane of the substrate surface. The cross-sectional and plane view of the double-gate structure are shown in FIGS. 1B and 1C, respectively. U.S. Pat. No. 6,413,802B1, however, does not teach the geometry end structure of contacts to the source and drain regions 22,24. U.S. Pat. No. 6,413,802B1 also does not teach a method of forming contacts with the source and drain regions 22,24 of the double-gate transistor 10. In fact, the fins 20 constituting the double-gate device of U.S. Pat. No. 6,413,802B1 each has an end connected to a source island and the other end connected to a drain island. In a paper by S. H. Tang, et al., entitled “FINFET—A quasi-planar double-gate MOSFET”, published at the 2001 IEEE International Solid State Circuits Conference, San Francisco, Calif., pp. 118–119, a double-gate FinFET structure with source/drain contacts made along the sides and the end of the fin was mentioned. However, the paper did not teach a method of forming contacts with the fin on the sidewalls.
An example of a multiple-gate transistor with three gates is the triple-gate transistor. The cross-section of the triple-gate transistor 30 is illustrated in FIGS. 2A and 2B. The plane view of the triple-gate transistor 30 is shown in FIG. 2C. The triple-gate transistor 30 is also shown in FIG. 3A. The triple-gate transistor 30 achieves better gate control than the double-gate device because it has one more gate 32 on the top of the silicon fin. In a paper by R. Chau et al., entitled “Advanced depleted-substrate transistors: single-gate, double-gate, and tri-gate”, published at the 2002 International Conference on Solid State Devices and Materials, Nagoya, Japan, pp. 68–69, September. 2002, a triple-gate transistor was reported. In that paper, the fins constituting the triple-gate transistor each has an end connected to a source island and the other end connected to a drain island. Contacts to the source and drain regions were formed on the top surface of the source and drain islands, respectively.
Yet another example of the multiple-gate transistor is the omega field-effect transistor, or the omega-FET. The omega-FET is an improved triple-gate transistor structure and has the closest resemblance to the Gate-All-Around (GAA) transistor for excellent scalability, and uses a very manufacturable process similar to that of the double-gate or triple-gate transistor. The omega-FET has a gate electrode with a omega-shaped cross-section (FIG. 2B). A three-dimensional perspective view of an omega-FET is shown in FIG. 3B.
While there is some work on the design and fabrication of multiple-gate devices such as the double-gate and triple-gate devices, there is little work focusing on the improvement or reduction of contact resistance in such devices. Contact resistance is a major fraction of the series resistance in nanoscale devices. Series resistance acts to reduce the drive current and the speed performance of transistors. The higher the series resistance, the lower the drive current for a given supply voltage. There is an increasing concern about the series resistance being a factor that degrades speed performance for CMOS scaling into the nanometer regime. The aforementioned multiple-gate devices have a common feature: a semiconductor fin.
Transistors with two or more gates, including the double-gate transistor, the triple-gate transistor, and the omega-FET, are termed “multiple-gate transistors”. The present invention relates to the provision of low resistance contacts to the source and drain regions in multiple-gate transistors. A common feature of the multiple-gate transistor, as illustrated in FIGS. 1A–3B, is the semiconductor fin constituting the transistor body. The semiconductor fin may be an elemental semiconductor such as silicon or germanium, an alloy semiconductor such as silicon-germanium, or a compound semiconductor such as indium phosphide and gallium arsenide. In the preferred embodiment, the semiconductor is silicon. The semiconductor fin found in the double-gate, triple-gate, and omega-FET device structures has three surfaces: a top surface and two sidewall surfaces. Another common feature of the transistors is that they are provided on semiconductor-on-insulator substrates. The insulator may be comprised of a dielectric such as silicon oxide, silicon nitride, or aluminum oxide.
In a conventional transistor, contact holes typically expose only one planar surface of the source ad drain regions. Therefore, conductive material filling the contact holes make contact with the source and drain regions at one planar surface. In fact, a prior art triple-gate transistor 40 adopted the traditional source and drain contact structure where the contacts to the source and drain regions are made at the top surface of the silicon, as shown in a plane view in FIG. 4. In FIG. 4, three silicon fins 42,44,46 are schematically shown. The silicon fins 42,44,46 are each connected to a source island 48 on one end and to the drain island 50 on the other end. A three-dimensional perspective view of a portion of the structure 40 of FIG. 4 is illustrated in FIG. 5. Contact holes are made to expose the top surfaces 52,54 of the source and drain islands 48,50 so that conductive materials 56 filling the contact holes make contact with the top surfaces 52,54 of the source and drain islands 48,50. More specifically, the contact surface 52,54 (or top surfaces) between the conductive material 56 and the source or drain islands 48,50 lay on a planar surface.
It is therefore an object of the present invention to provide an improved method of forming multiple-gate transistors with low series resistance.
It is yet another object of the present invention to provide a method of forming a low contact resistance and large contact area in multiple-gate transistors.